Verilog by Example

A Concise Introduction for FPGA Design

Omschrijving

A practical primer for the student and practicing engineer already familiar with the basics of digital design, the reference develops a working grasp of the verilog hardware description language step-by-step using easy-to-understand examples. Starting with a simple but workable design sample, increasingly more complex fundamentals of the language are introduced until all major features of verilog are brought to light. Included in the coverage are state machines, modular design, FPGA-based memories, clock management, specialized I/O, and an introduction to techniques of simulation. The goal is to prepare the reader to design real-world FPGA solutions. All the sample code used in the book is available online. What Strunk and White did for the English language with The Elements of Style, VERILOG BY EXAMPLE does for FPGA design.
€ 26,55
Paperback / softback
 
Gratis verzending vanaf
€ 19,95 binnen Nederland
Schrijver
Readler, Blaine
Titel
Verilog by Example
Uitgever
Full ARC Press
Jaar
2011
Taal
Engels
Pagina's
124
Gewicht
200 gr
EAN
9780983497301
Afmetingen
222 x 152 x 13 mm
Bindwijze
Paperback / softback

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