This book constitutes the refereed proceedings of the 7th International Workshop on Systems, Architectures, Modeling, and Simulation, SAMOS 2007, held in Samos, Greece in July 2007. The 44 revised full papers presented together with 2 keynote talks were thoroughly reviewed and selected from 116 submissions. The papers are organized in topical sections on system modeling and simulation, VLSI architectures, scheduling and programming models, multi-processor architectures, reconfigurable architectures, design space exploration, processor components, embedded processors, SoC for SDR, and wireless sensors. Stamatis Vassiliadis established the SAMOS workshop in the year 2001¿an event which combines his devotion to computer engineering and his pride for Samos, the island where he was born. The quiet and inspiring northern mo- tainside of this Mediterranean island together with his enthusiasm and warmth created a unique atmosphere that made this event so successful. Stamatis V- siliadis passed away on Saturday, April 7, 2007. The research community wants to express its gratitude to him for the creation of the SAMOS workshop, which will not be the same without him. We would like to dedicate this proceedings volume to the memory of Stamatis Vassiliadis. The SAMOS workshop is an international gathering of highly quali?ed - searchers from academia and industry, sharing their ideas during a 3-day lively discussion.Theworkshopmeetingisoneoftwocolocatedevents¿theotherevent being the IC-SAMOS. The workshop is unique in the sense that not only solved research problems are presented and discussed but also (partly) unsolved pr- lems and in-depth topical reviews can be unleashed in the scienti?c arena. C- sequently, the workshop provides the participants with an environment where collaboration rather than competition is fostered. Keynotes Software Is the Answer But What Is the Question? 1 Willie Anderson Integrating VLIW Processors with a Network on Chip 2 Jos Huisken System Modeling and Simulation Communication Architecture Simulation on the Virtual Synchronization Framework 3 Taewook Oh, Youngmin Yi, and Soonhoi Ha A Model-Driven Automatically-Retargetable Debug Tool for Embedded Systems 13 Max R. de O. Schultz, Alexandre K.I. Mendon Felipe G. Carvalho, Olinto J.V. Furtado, and Luiz C.V. Santos Performance Evaluation of Memory Management Configurations in Linux for an OS-Level Design Space Exploration 24 Sangsoo Park and Heonshik Shin SC2SCFL: Automated SysteniC to SystemCFL Translation 34 Ka Lok Man, Andrea Fedeli, Michele Mercaldi, Menouer Boubekeur, and Michel Schellekens VLSI Architectures Model and Validation of Block Cleaning Cost for Flash Memory 46 Seungjae Back, Jonginoo Choi, Donghee Lee, and Sam H. Noh VLSI Architecture for MRF Based Stereo Matching 55 Sungchan Park, Chao Chen, and Hong Jeong Low-Power Twiddle Factor Unit for FFT Computation 65 Teemu Pitk n, Tero Partanen, and Jarmo Takata Trade-Offs Between Voltage Scaling and Processor Shutdown for Low-Energy Embedded Multiprocessors 75 Pepijn de Langen and Ben Juurlink Scheduling & Programming Models An Automatically-R,etargetable Time-Constraint-Driven Instruction Scheduler for Post-compiling Optimization of Embedded Code 86 Jos . Carlomagno F., Luiz F.P. Santos, and Luiz C.V. dos Santos Improving TriMedia Cache Performance by Profile Guided Code Reordering 96 Norbert Esser, Renga Sundararajan, and Joachim Trescher A Streaming Machine Description and Programming Model 107 Paul Carpenter, David Rodenas, Xavier Martorell, Alex Ramirez, and Eduard Ayguad TD> Multi-processor Architectures Mapping and Performance Evaluation for Heterogeneous MP-SoCs Via Packing 117 Bastian Ristau and Gerhard Fettweis Strategies for Compiling ?TC to Novel Chip Multiprocessors 127 Thomas A.M. Bernard, Chris R. Jesshope, and Peter M.W. Knijnenburg Image Quantisation on a Massively Parallel Embedded Processor 139 Jan Jacobs, Leroy van Engelen, Jan Kuper, and Gerard J.M. Smit Stream Image Processing on a Dual-Core Embedded System 149 Michael G. Benjamin and David Kaeli Reconfigurable Architectures MORA: A New Coarse-Grain Reconfigurable Array for High Throughput Multimedia Processing 159 Marco Lanuzza, Stefania Perri, and Pasquale Corsonello FPGA Design Methodology for a Wavelet.-Based Scalable Video Decoder 169 Hendrik Eeckhaut, Harald Devos, Philippe Faes, Mark Christiaens, and Dirk Stroobandt Evaluating Large System-on-Chip on Multi-FPGA Platform 179 Ari Kulmala, Erno Salminen, and Timo D. H l en Design Space Exploration Efficiency Measures for Multimedia SOCs 190 Hartwig Jeschke On-Chip Bus Modeling for Power and Performance Estimation 200 Je-Hoon Lee, Young-Shin Cho, Seok-Man Kim, and Kyoung-Rok Cho A Framework Introducing Model Reversibility in SoC Design Space Exploration 211 Alexis Vander Biest, Alienor Richard, Dragomir Milojevic, and Frederic Robert Towards Multi-application Workload Modeling in Sesame for System-Level Design Space Exploration 222 Mark Thompson and Andy D. Pimentel Processor Components Resource Conflict Detection in Simulation of Function Unit Pipelines 233 Pekka J kel en, Vladimir Guzma, and Jarmo Takala A Modular Coprocessor Architecture for Embedded Real-Time Image and Video Signal Processing 241 Holger Flatt, Sebastian Hesselbarth, Sebastian Fl gel, and Peter Pirsch High-Bandwidth Address Generation Unit 251 Humberto Calder n, Carlo Galuzzi, Georgi Gaydadjiev, and Stamatis Vassiliadis An IP Core for Embedded Java Systems 263 Sascha Uhrig, J rg Mische, and Theo Ungerer Embedded Processors Parallel Memory Architecture for TTA Processor 273 Jarno Tanskanen, Teemu Pitk n, Risto M nen, and Jarmo Takala A Linear Complexity Algorithm for the Generation of Multiple Input Single Output Instructions of Variable Size 283 Carlo Galuzzi, Koen Bertels, and Stamatis Vassiliadis Automated Power Gating of Registers Using CoDeL and FSM Branch Prediction 294 Nainesh Agarwal and Nikitas J. Dimopoulos A Study of Energy Saving in Customizable Processors 304 Paolo Zonzini, Dilek Harmanci, and Laura Pozzi SoC for SDR Trends in Low Power Handset Software Defined Radio 313 John Glossner, Daniel Iancu, Mayan Moudgill, Michael Schulte, and Stamatis Vassiliadis Design of a Low Power Pre-synchronization ASIP for Multimode SDR Terminals 322 Thomas Schuster, Bruno Bougard, Praveen Raghavan, Robert Priewasser, David Novo, Liesbet Van der Perre, and Francky Catthoor Area Efficient Fully Programmable Baseband Processors 333 Anders Nilsson and Dake Liu The Next Generation Challenge for Software Defined Radio 343 Mark Woh, Sangwon Seo, Hyunseok Lee, Yuan Lin, Scott Mahlke, Trevor Mudge, Chaitali Chakrabarti, and Krisztian Flautner Design Methodology for Software Radio Systems 355 Chia-han Lee and Wayne Wolf Power Efficient Co-simulation Framework for a Wireless Application Using Platform Based SoC 365 Tseesuren Batsuuri, Je-Hoon Lee, and Kyoung-Rok Cho A Comparative Study of Different FFT Architectures for Software Defined Radio 375 Shashank Mittal, Md. Zafar Ali Khan, and M.B. Srinivas Wireless Sensors Design of 100?W Wireless Sensor Nodes on Energy Scavengers for Biomedical Monitoring 385 Lennart Yseboodt, Michael De Nil, Jos Huisken, Mladen Berekovic, Qin Zhao, Frank Bouwens, and Jef Van Meerbergen Tool-Aided Design and Implementation of Indoor Surveillance Wireless Sensor Network 396 Maori Kuorilehto, Jukka Suhonen, Marko H ik en, and Timo D. H l en System Architecture Modeling of air UWB Receiver for Wireless Sensor Network 408 Aubin Lecointre, Daniela Dragomirescu, and Robert Plana An Embedded Platform with Duty-Cycled Radio and Processing Subsystems for Wireless Sensor Networks 421 Zhong-Yi fin, Curt Schurgers, and Rajesh Gupta SensorOS: A New Operating System for Time CriticalWSN Application 431 Kuorilehto, Timo Alho, Marko H ik en, and Inno D. H l en Review of Hardware Architectures for Advanced Encryption Standard Implementations Considering Wireless Sensor Networks 443 Panu H l en, Marko H ik en, and Timo D. H l en k+ Neigh: An Energy Efficient Topology Control for Wireless Sensor Networks 454 Dong-Min Son and Young-Bae Ko Author Index 465