This book constitutes the refereed proceedings of the 12th Asia-Pacific Computer Systems Architecture Conference, ACSAC 2007, held in Seoul, Korea in August 2007. The 26 revised full papers presented together with 2 keynote 8 invited lectures were carefully reviewed and selected from 92 submissions. The papers encompass a wide range of topics, with much emphasis in hardware and software techniques for state-of-the-art multicore and multithreaded architectures. On behalf of the program and organizing committee members of this conference, we th are pleased to present you with the proceedings of the 12 Asia-Pacific Computer Systems Architecture Conference (ACSAC 2007), which was hosted in Seoul, Korea on August 23-25, 2007. This conference has traditionally been a forum for leading researchers in the Asian, American and Oceanian regions to share recent progress and the latest results in both architectural and system issues. In the past few years the c- ference has become more international in the sense that the geographic origin of p- ticipants has become broader to include researchers from all around the world, incl- ing Europe and the Middle East. This year, we received 92 paper submissions. Each submission was reviewed by at least three primary reviewers along with up to three secondary reviewers. The total number of completed reviews reached 333, giving each submission 3.6 reviews on average. All the reviews were carefully examined during the paper selection process, and finally 26 papers were accepted, resulting in an acceptance rate of about 28%. The selected papers encompass a wide range of topics, with much emphasis on hardware and software techniques for state-of-the-art multicore and multithreaded architectures. A Compiler Framework for Supporting Speculative Multicore Processors (Keynote) 1 Pen-Chung Yew Power-Efficient Heterogeneous Multicore Technology for Digital Convergence (Keynote) 2 Kunio Uchiyama StarDBT: An Efficient Multi-platform Dynamic Binary Translation System 4 Cheng Wang, Shiliang Hu, Ho-seop Kim, Sreekumar R. Nair, Mauricio Breternitz Jr., Zhiwei Ying, and Youfeng Wu Unbiased Branches: An Open Problem 16 Arpad Gellert, Adrian Florea, Maria Vintan, Colin Egan, and Lucian Vintan An Online Profile Guided Optimization Approach for Speculative Parallel Threading 28 Yuan Liu, Hong An, Bo Liang, and Li Wang Entropy-Based Profile Characterization and Classification for Automatic Profile Management 40 Jinpyo Kim, Wei-Chung Hsu, Pen-Chung Yew, Sreekumar R. Nair, and Robert Y. Geva Laplace Transformation on the FT64 Stream Processor 52 Yu Deng, Xuejun Yang, Xiaobo Yan, and Kun Zeng Towards Data Tiling for Whole Programs in Scratchpad Memory Allocation 63 Lian Li, Hui Wu, Hui Feng, and Jingling Xue Evolution of NAND Flash Memory Interface 75 Sang Lyul Min, Eyee Hyun Nam, and Young Hee Lee FCC-SDP: A Fast Close-Coupled Shared Data Pool for Multi-core DSPs 80 Dong Wang, Xiaowen Chen, Shuming Chen, Xing Fang, and Shuwei Sun Exploiting Single-Usage for Effective Memory Management 90 Thomas Piquet, Olivier Rochecouste, and Andr eznec An Alternative Organization of Defect Map for Defect-Resilient Embedded On-Chip Memories 102 Kang Yi, Shih-Yang Cheng, Young-Hwan Park, Fadi Kurdahi, and Ahmed Eltawil An Effective Design of Master-Slave Operating System Architecture for Multiprocessor Embedded Systems 114 Minyeol Seo, Ha Seok Kim, Ji Chan Maeng, Jimin Kim, and Minsoo Ryu Optimal Placement of Frequently Accessed IPs in Mesh NoCs 126 Reza Moraveji, Hamid Sarbazi-Azad, and Maghsoud Abbaspour An Efficient Link Controller for Test Access to IP Core-Based Embedded System Chips 139 Jaehoon Song, Hyunbean Yi, Juhee Han, and Sungju Park Performance of Keyword Connection Algorithm in Nested Mobility Networks 151 Sang-Hoon Ryu and Doo-Kwon Baik Leakage Energy Reduction in Cache Memory by Software Self-invalidation 163 Kiyofumi Tanaka and Takenori Fujita Exploiting Task Temperature Profiling in Temperature-Aware Task Scheduling for Computational Clusters 175 Daniel C. Vanderster, Amirali Baniasadi, and Nikitas J. Dimopoulos Runtime Performance Projection Model for Dynamic Power Management 186 Sang-Jeong Lee, Hae-Kag Lee, and Pen-Chung Yew A Power-Aware Alternative for the Perceptron Branch Predictor 198 Kaveh Aasaraai and Amirali Baniasadi Power Consumption and Performance Analysis of 3D Noes 209 Akbar Sharifi and Hamid Sarbazi-Azad A Design Methodology for Performance-Resource Optimization of a Generalized 2D Convolution Architecture with Quadrant Symmetric Kernels 220 Ming Z. Zhang and Vijayan K. Asari Bipartition Architecture for Low Power JPEG Huffman Decoder 235 Shang-fang Ruan and Wei-Te Lin A SWP Specification for Sequential Image Processing Algorithms 244 Wensheng Tang, Shaogang Wang, Dan Wu, and Wangqiu Kuang A Stream System-on-Chip Architecture for High Speed Target Recognition Based on Biologic Vision 256 Nan Wu, Qianming Yang, Mei Wen, Yi He, Changqing Xun, and Chunyuan Zhang FPGA-Accelerated Active Shape Model for Real-Time People Tracking 268 Yong Dou and Jinbo Xu Performance Evaluation of Evolutionary Multi-core and Aggressively Multi-threaded Processor Architectures 280 Partha Tirumalai, Yonghong Song, and Spiros Kalogeropulos Synchronization Mechanisms on Modern Multi-core Architectures 290 Shaoshan Liu and Jean-Luc Gaudiot Concerning with On-Chip Network Features to Improve Cache Coherence Protocols for CMPs 304 Hongbo Zeng, Kun Huang, Ming Wu, and Weiwu Hu Generalized Wormhole Switching: A New Fault-Tolerant Mathematical Model for Adaptively Wormhole-Routed Interconnect Networks 315 P. Safaei, A. Khonsari, M. Fathy, N. Talebanfard, and AL Ould-Khaoua Open Issues in MPI Implementation 327 Rajeev Thakur and William Gropp Implicit Transactional Memory in Kilo-Instruction Multiprocessors 339 Marco Galluzzi, Enrique Vallejo, Adri Cristal, Fernando Vallejo, Ram n Beivide, Per Stenstr m, James E. Smith, and Mateo Valero Design of a Low Power Embedded Processor Architecture Using Asynchronous Function Units 354 Yong Li, Zhiying Wang, Xuemi Zhao, Jian Ruan, and Kui Dai A Bypass Mechanism to Enhance Branch Predictor for SMT Processors 364 Yongfeng Pan, Xiaoya Fan, Liqiang He, and Deli Wang Thread Priority-Aware Random Replacement in TLBs for a High-Performance Real-Time SMT Processor 376 Emre er and Stuart Biles Architectural Solution to Object-Oriented Programming 387 Tan Yiyu, Anthony S. Fong, and Yang Xiaojian Author Index 399